1. Field of the Invention
The present invention relates to a pattern management method of extracting and managing a critical pattern that is likely to lead to a defect from a chip layout of an integrated circuit.
Specifically, in a photolithography step and a processing step, this method is used for a design, an improvement in a systematic error of optical proximity correction (OPC), enhancement of a simulation technology and of a production yield of a production line, and stabilization of a process margin. In particular, it is used to develop a mask technology, improve the simulation technology, and manage process manufacture in the photolithography step.
2. Description of the Related Art
In mask development in a photolithography step, simulation or check of a design rule of OPC are conventionally performed in accordance with each generation to correct and optimize a critical pattern which becomes a hotpot. Specifically, a mask finished according to a design is created based on OPC simulation, subjected to a trial production in a plant side (on a production line), and subjected to a mass production if it can meet expectations. However, taking a measure against a defective pattern position on an initial stage and developing each mask strictly based on the design rule are becoming difficult when the design rule tightens (see, e.g., JP-A 2004-184633 [KOKAI]).
In regard to a pattern in a chip surface which has insufficiently process margin and is likely to fluctuate in particular, a degree of an influence thereof cannot be estimated, and an electrical defect (an open circuit or a short circuit) occurs. In this case, since a production yield is not stabilized until mass production is started and process conditions are determined, many defective products are produced, which leads to a waste of time, that is, long turn-around time (TAT).
Further, since a lot is managed with a small process margin, a fluctuation in the process provokes a low production yield because of an influence of an unknown critical position. In order to extract such a pattern having insufficient process margin at such a critical position, running a production yield confirmation lot is indispensable to find the position with the low production yield and analyze the defect. Therefore, a long time and many engineers are required for optimization of the process condition.
As explained above, according to the conventional technology, a systematic critical position, which cannot be detected by checking based on a design rule, is generated in regard to a newly introduced product, a product based on a strict design rule, and an existing product having no stabilized production yield, and this becomes a factor of the low production yield. Furthermore, there is a problem of requiring big chunks of time and cost until a critical position which becomes a hotpot affecting a production yield is detected. Moreover, there is another problem that a critical position cannot be specified because of an issue of a detection sensitivity of an inspection device due to an influence of a process, even though the critical pattern is extracted on a wafer subjected to pattern formation based on photolithography, and each product cannot be stably supplied.
Additionally, in mask development in the photolithography step, specifying a critical position in a pattern is difficult, resulting in a reduction in a production yield and a process margin.
Therefore, it is desired that realization of a pattern management method which can readily extract a critical pattern likely leading to a defect from a chip layout of an integrated circuit, and can contribute to improving a production yield and stabilize a process margin.